The present invention relates to a delay locked loop (DLL) circuit.
A DLL circuit is a circuit to control a timing of data output from a synchronous memory device by using an external clock signal.
In order to transfer output data of the memory device to a chipset without error, the memory device and the chipset should operate in synchronization with a clock signal. However, a phase difference occurs between an external clock and an internal clock because the external clock input to the memory device is delayed by internal circuits. A DLL circuit eliminates a phase difference between output data of the memory device and the external clock by compensating for clock skew occurring due to internal circuits.
FIG. 1 is a block diagram of a conventional DLL circuit.
Referring to FIG. 1, the conventional DLL circuit includes a phase comparator 103, a delay line 105, a delay controller 107, and a replica model 109.
The phase comparator 103 compares the phase of an external clock EXT_CLK with the phase of a feedback clock FB, which is fed back from the replica model 109, to detect the phase difference between the two clocks. The phase comparator 103 generates a control signal according to the detected phase difference. The delay controller 107 is implemented with a shift register, and determines amount of delay, that is, a shift direction and a shift amount of the external clock EXT_CLK, based on the detected phase difference, to control the delay line 105 according to the determined amount of delay. The external clock EXT_CLK input to the delay line 105 is delayed according to the amount of delay determined by the delay controller 107. The replica model 109 includes modeled clock delay components of the internal paths of the memory device. The replica model 109 delays the external clock EXT_CLK delayed by the delay line 105 according to the modeling of the replica model 109, and outputs the feedback clock FB to the phase comparator 103.
Through the above procedures, the external clock EXT_CLK is delayed by the delay line 105 and output as the feedback clock FB by the replica model 109. A phase of the feedback clock FB coincides with that of the external clock EXT_CLK. This is called a delay locking.
The amount of delay of the delay line 105, which is determined by the delay controller 107, is expressed as the following Equation 1.DD=N×TEXT−DFB   Eq. 1where DD is the amount of delay of the delay line 105, that is, the amount of delay of the external clock EXT_CLK, TEXT is the period of the external clock EXT_CLK, DFB is the amount of delay of the feedback clock FB output from the replica model 109, and N is an integer determined according to design.
FIG. 2 is a timing diagram illustrating the amount of delay DD determined by a delay controller 107 of FIG. 1. Referring to FIG. 2, when the period TEXT of the external clock EXT_CLK is 5; N is 1; and the amount of delay DFB of the feedback clock FB output from the replica model 109 is 3, the amount of delay DD of the delay line 105 is 2. That is, the external clock EXT_CLK delayed by the amount of delay DD of the delay line 105 is output as the feedback clock FB through the replica model 109, and the phase of the feedback clock FB coincides with the phase of the external clock EXT_CLK. At this point, the amount of delay DD is locked.
According to the related art, the amount of delay DFB of the feedback clock FB output from the replica model 109 is influenced by a variety of factors, for example, a variation of a power source. If the amount of delay DFB of the feedback clock FB output from the replica model 109 increases, it becomes greater than the fixed value “N×TEXT” of Equation 1 and thus the locking may not be achieved.
To solve the above problem, the value of N should be increased. However, if the value of N is increased, the amount of delay DD of the delay line 105 also increases. Thus, a locking time increases and jitters are generated.